Although much research and development effort is devoted to aspects of integrated circuit technology such as the devices in the circuit and their operating speeds, other aspects of integrated circuit technology are of equal importance for progress within the field of integrated circuits. Specifically, power distribution through existing integrated circuit devices has hampered further development within the field. For example, due to technological developments, as power consumption increases above several watts in a given device, voltage levels decrease to 1.2 V or lower. It is this power distribution voltage drop in large integrated circuit designs that has become a problem of increasing importance.
In order to improve the power distribution of an integrated circuit device, the current method of power distribution and elements of an integrated circuit device involved in power distribution must first be understood. A positive voltage supply ring and a negative voltage supply ring typically surround the periphery of a die of an integrated circuit device. Positive voltage supply and negative voltage supply connections are made from the positive voltage supply ring and the negative voltage supply ring to bond pads along the periphery of the die via bond wires. These positive voltage supply and negative voltage supply bond pads are typically disposed among those bond pads used to transmit signals from the integrated circuit device to a leadframe, ball grid array package, pin grid array package or other packaging structure. The power must be distributed through internal points of the integrated circuit device from these positive voltage supply and negative voltage supply bond pads along the periphery of the die. It is this distribution or connection that significantly drops the power distribution voltage levels of the integrated circuit device.
Power is routed from the bond pads on the periphery through metal lines in the integrated circuit device. However, due to the fact that these metal lines may not cross over or contact other metal connectors for circuits or other elements of the integrated circuit device, the metal lines may be forced to take longer and more complicated routes to reach the interior area of the integrated circuit device. Further, in order for a sufficient amount of power to be provided to the interior of the integrated circuit device, a metal line or other type of internal bus must be significantly thicker than the ordinary metal connectors. Once power is provided to the interior region of the integrated circuit device, local power interconnects of significantly smaller size may distribute the power to circuit elements. Power distribution voltage drop occurs when there is a high resistivity, thereby reducing the efficiency of the integrated circuit device. The complicated and unnecessarily long routing paths for the power, and the inability to provide a large enough bus to the interior region of the integrated circuit device contribute to the power distribution voltage drop.
Presently, attempts to solve the power distribution voltage drop problem include the utilization of more metal layers in the integrated circuit device. The additional layers may allow for more direct routing of the metal lines and easier access to the interior region of the integrated circuit device. However, the addition of metal layers to the integrated circuit device increases the cost of wafer processing and may not adequately address the problem of power distribution voltage drop, even when utilized to its maximum extent. Integrated circuit devices with more layers have lower reliability since there is a greater possibility of defects. When additional metal layers do not resolve the power distribution voltage drop problem, flip-chip packaging technology has been utilized. However, flip-chip packaging further increases integrated circuit processing cost because it utilizes a solder bumping process and more expensive package substrates.
Further developments in integrated circuit devices are demonstrated in U.S. Pat. No. 5,751,065, entitled “Integrated Circuit with Active Devices Under Bond Pads,” which is incorporated herein by reference. Due to conventional bonding technology used to attach wires to bond pads, and to design constraints, bond pads typically have relatively large dimensions as compared to the device dimension and occupy or cover a significant portion of the chip surface. The area underneath the bond pads thus occupies a substantial fraction of the entire chip surface. Techniques disclosed in the above-cited patent allow active circuitry to be placed under bond pads in an integrated circuit having at least three metal layers. The metal layer adjacent the bond pad layer acts as a buffer, provides stress relief, and prevents leakage currents between the bond pad and underlying circuitry. Although the disclosed techniques provide more room for circuitry, they do not directly address the problem of excessive power distribution voltage drop.
Thus, a need exits for techniques that reduce the voltage drop associated with power distribution in an integrated circuit device without significantly increasing integrated circuit device processing cost.